1. Field of the Invention
This invention relates to a three-dimensional semiconductor integrated circuit device, in which multi-layered functional device arrays are formed on a semiconductor substrate with an electronic circuit formed, especially to a vertical wiring structure for drawing the signal lines in the functional device arrays to the substrate.
2. Description of the Related Art
It has been proposed such a resistance change memory (ReRAM) that stores a resistance value as data, which is reversibly exchanged by applying voltage, current or heat, and it is noticed for succeeding to the conventional NAND-type flash memory. This resistance change memory is suitable for shrinking the cell size, and for constituting a cross-point cell array. In addition, it is easy to stack cell arrays. Therefore, ReRAM is expected to be constituted as a large capacitive file memory with a three dimensional (3D-) cell array structure.
Especially, a unipolar type of ReRAM cell has such a feature that the high resistance state and low resistance state are reversibly settable by controlling the applied voltage and applying time thereof. For example, refer to Y. Hosoi et al, “High Speed Unipolar Switching Resistance RAM(RRAM) Technology” IEEE International Electron Devices Meeting 2006, Technical Digest, P. 793-796.
What is problematic in case of achieving a 3D-cell array structure is in the vertical wiring (i.e., via-wiring) structure, which serves for receiving/transmitting signals between the control circuit formed on the semiconductor substrate and the cell arrays stacked thereon. Each memory cell array is formed of word lines, bit lines formed with the minimum pitch, and a set of memory cells disposed at the respective cross-points. It is required of the word lines and bit lines to be coupled to the substrate via the vertical wirings disposed at the end portions of the word lines and bit lines.
The vertical wirings may be formed simply in such a way as to bury metal layers in contact holes formed in an insulating layer. However, as the number of stacked layers of the 3D-cell array increases, and as the integration progresses, not only the word line pitch and bit line pitch are made to be smaller, but also the contact hole becomes smaller in size and deeper. Therefore, lithography step and etching step for forming the contact holes, and deposition step for burying a metal layer in the contact holes become difficult. Specifically, the vertical wiring portion is difficult to shrink in comparison with the cell array portion, and there is a probability that this becomes a bottle neck for constituting the whole memory device.